Difference between revisions of "Instruction Set/shiftluwv"
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{{DISPLAYTITLE:shiftluwv}} | {{DISPLAYTITLE:shiftluwv}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Overflow|using widening overflow behavior]] [[Condition Code|that produces condition codes]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | bitwise shift | + | Unsigned bitwise vector left shift. Widening. |
| + | The bit count by which to shift is an unsigned number. | ||
| + | The higher order bits get zero extended in the widening. | ||
| + | Produces two result vectors. | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">shiftluwv</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) → [[Domains#u|u]] r<sub>0</sub>, [[Domains#u|u]] r<sub>1</sub></code> | <code style="font-size:130%"><b style="color:#050">shiftluwv</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#bit|bit]]</span> <span title="bit number">bits</span></i>) → [[Domains#u|u]] r<sub>0</sub>, [[Domains#u|u]] r<sub>1</sub></code> | ||
Latest revision as of 09:29, 9 February 2015
speculable exu stream exu block compute phase operation in the unsigned integer value domain using widening overflow behavior that produces condition codes
native on: all
Unsigned bitwise vector left shift. Widening. The bit count by which to shift is an unsigned number. The higher order bits get zero extended in the widening. Produces two result vectors.
shiftluwv(u x, bit bits) → u r0, u r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 | 2 2 |
| Silver | E0 E1 | 2 2 |
| Gold | E0 E1 | 2 2 |
| Decimal8 | E0 E1 | 2 2 |
| Decimal16 | E0 E1 | 2 2 |
shiftluwv(u x, n bits) → u r0, u r1
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 | 2 2 |
| Silver | E0 E1 | 2 2 |
| Gold | E0 E1 | 2 2 |
| Decimal8 | E0 E1 | 2 2 |
| Decimal16 | E0 E1 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
