Difference between revisions of "Instruction Set/roots"
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m (Protected "Instruction Set/roots": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite))) | |||
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{{DISPLAYTITLE:roots}} | {{DISPLAYTITLE:roots}} | ||
− | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed integer value domain]] [[Condition Code|that produces condition codes]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
− | square root | + | Signed integer square root. Helper operation for software square root implementation. |
+ | |||
+ | This operation creates a seed value for Newton-Rapheson, or other, iterative methods. | ||
+ | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">roots</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#s|s]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">roots</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#s|s]] r<sub>0</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding#roots|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#roots|Tin]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
− | + | ||
− | + | ||
− | + | ||
− | + | ||
|- | |- | ||
− | | [[Cores/ | + | | [[Cores/Copper/Encoding#roots|Copper]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
|- | |- | ||
− | | [[Cores/ | + | | [[Cores/Silver/Encoding#roots|Silver]] || E0 E1 E2 E3 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
|- | |- | ||
− | | [[Cores/ | + | | [[Cores/Gold/Encoding#roots|Gold]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 14:04, 23 February 2021
speculable exu stream exu block compute phase operation in the signed integer value domain that produces condition codes
native on: all
Signed integer square root. Helper operation for software square root implementation.
This operation creates a seed value for Newton-Rapheson, or other, iterative methods.
operands: like Identity [xx:x]
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
Copper | E0 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
Silver | E0 E1 E2 E3 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
Gold | E0 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable