Difference between revisions of "Instruction Set/u2s"
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{{DISPLAYTITLE:u2s}} | {{DISPLAYTITLE:u2s}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the logical value domain]] [[Overflow|using modulo overflow behavior]] <br /> |
| − | '''aliases:''' | + | '''aliases:''' u2s2 <br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
| − | + | Unsigned integer to signed integer. | |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">u2s</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#op|op]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">u2s</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#op|op]] r<sub>0</sub></code> | ||
| Line 12: | Line 13: | ||
<br /> | <br /> | ||
| + | '''encoding:''' | ||
| + | <code style="font-size:100%"><b style="color:#050">u2s</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>)</code> | ||
| + | <br /> | ||
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
| Line 17: | Line 21: | ||
| [[Cores/Tin/Encoding#u2s|Tin]] || E0 || 1 | | [[Cores/Tin/Encoding#u2s|Tin]] || E0 || 1 | ||
|- | |- | ||
| − | | [[Cores/Copper/Encoding#u2s|Copper]] || E0 | + | | [[Cores/Copper/Encoding#u2s|Copper]] || E0 || 1 |
|- | |- | ||
| [[Cores/Silver/Encoding#u2s|Silver]] || E0 E1 E2 E3 || 1 | | [[Cores/Silver/Encoding#u2s|Silver]] || E0 E1 E2 E3 || 1 | ||
|- | |- | ||
| − | | [[Cores/Gold/Encoding#u2s|Gold]] || E0 | + | | [[Cores/Gold/Encoding#u2s|Gold]] || E0 || 1 |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:02, 23 February 2021
speculable exu stream exu block compute phase operation in the logical value domain using modulo overflow behavior
aliases: u2s2
native on: all
Unsigned integer to signed integer.
operands: like Identity [xx:x]
encoding:
u2s(op x)
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 1 |
| Copper | E0 | 1 |
| Silver | E0 E1 E2 E3 | 1 |
| Gold | E0 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
