Difference between revisions of "Instruction Set/mulss"

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m (Protected "Instruction Set/mulss": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
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{{DISPLAYTITLE:mulss}}
 
{{DISPLAYTITLE:mulss}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using saturating overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using saturating overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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'''aliases:''' mulssv <br />
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'''aliases:''' mulss2 <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#mulss|Tin]] || E0 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Tin/Encoding#mulss|Tin]] || E0 ||  
 
|-
 
|-
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| [[Cores/Copper/Encoding#mulss|Copper]] || E0 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Copper/Encoding#mulss|Copper]] || E0 ||  
 
|-
 
|-
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| [[Cores/Silver/Encoding#mulss|Silver]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Silver/Encoding#mulss|Silver]] || E0 E1 ||  
 
|-
 
|-
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| [[Cores/Gold/Encoding#mulss|Gold]] || E0 E1 E2 E3 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Gold/Encoding#mulss|Gold]] || E0 ||  
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|}
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 +
----
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<code style="font-size:130%"><b style="color:#050">mulss</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#imm|imm]]</span> <span title="small immediate constant of per-slot varying range">imm0</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
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</div>
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<br />
 +
 
 +
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 +
|-
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| [[Cores/Tin/Encoding#mulss|Tin]] || E0 ||
 +
|-
 +
| [[Cores/Copper/Encoding#mulss|Copper]] || E0 ||
 
|-
 
|-
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| [[Cores/Decimal8/Encoding#mulss|Decimal8]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Silver/Encoding#mulss|Silver]] || E0 E1 ||  
 
|-
 
|-
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| [[Cores/Decimal16/Encoding#mulss|Decimal16]] || E0 E1 || b,b:b=3 bv,bv:bv=3 h,h:h=3 hv,hv:hv=3 w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=4 qv,qv:qv=4
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| [[Cores/Gold/Encoding#mulss|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:01, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using saturating overflow behavior   that produces condition codes

aliases: mulss2
native on: all

Signed Integer multiply. Saturating.

mulss(s x, s y) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1
Gold E0

mulss(s op0, imm imm0) → s r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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