Difference between revisions of "Instruction Set/addsw"

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m (Protected "Instruction Set/addsw": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
 
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{{DISPLAYTITLE:addsw}}
 
{{DISPLAYTITLE:addsw}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp; [[Overflow|using widening overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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----
 
----
 
<code style="font-size:130%"><b style="color:#050">addsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">addsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]]
 
</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#addsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Tin/Encoding#addsw|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#addsw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Copper/Encoding#addsw|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#addsw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Silver/Encoding#addsw|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#addsw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Gold/Encoding#addsw|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#addsw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#addsw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
 
|}
 
|}
  
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">addsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#imm|imm]]</span> <span title="small immediate constant of per-slot varying range">y</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">addsw</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">x</span>, <i><span style="color:#009">[[Immediates#imm|imm]]</span> <span title="small immediate constant of per-slot varying range">y</span></i>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWidening|like Widening xx:2x]]
 
</div>
 
</div>
 
<br />
 
<br />
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#addsw|Tin]] || E0 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Tin/Encoding#addsw|Tin]] || E0 ||  
−
|-
+
−
| [[Cores/Copper/Encoding#addsw|Copper]] || E0 E1 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
−
|-
+
−
| [[Cores/Silver/Encoding#addsw|Silver]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#addsw|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Copper/Encoding#addsw|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#addsw|Decimal8]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Silver/Encoding#addsw|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#addsw|Decimal16]] || E0 E1 E2 E3 || b,b:h=1 h,h:w=1 w,w:d=2 d,d:q=2
+
| [[Cores/Gold/Encoding#addsw|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:58, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the signed integer value domain   using widening overflow behavior   that produces condition codes

native on: all

Widening signed integer addition. When a result value overflows, it is widened.

addsw(s x, s y) → s r0

operands: like Widening xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

addsw(s x, imm y) → s r0

operands: like Widening xx:2x


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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