Difference between revisions of "Cores/Copper"
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{{DISPLAYTITLE:Copper Core}} | {{DISPLAYTITLE:Copper Core}} | ||
| − | <b>[[Cores]]:</b> [[Cores/Tin|Tin]] [[Cores/Copper|Copper]] [[Cores/Silver|Silver]] [[Cores/Gold|Gold | + | <b>[[Cores]]:</b> [[Cores/Tin|Tin]] [[Cores/Copper|Copper]] [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] |
The Copper core isn't much bigger than Tin, but here both flow and exu slots are properly populated with functional units, so instruction level parallelism is approximately doubled in comparison. Mobile devices, low power servers or smart devices like printers are the expected primary targets. | The Copper core isn't much bigger than Tin, but here both flow and exu slots are properly populated with functional units, so instruction level parallelism is approximately doubled in comparison. Mobile devices, low power servers or smart devices like printers are the expected primary targets. | ||
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<b>[[Belt]]</b>: 8 <b>[[Decode#Morsel|Morsel]]</b>: 3bit <b>[[Operands|Scalar Width]]</b>: 64bit <b>[[Operands|Operand Maximum Size]]</b>: 8B | <b>[[Belt]]</b>: 8 <b>[[Decode#Morsel|Morsel]]</b>: 3bit <b>[[Operands|Scalar Width]]</b>: 64bit <b>[[Operands|Operand Maximum Size]]</b>: 8B | ||
| − | <b>[[Pipeline]]s</b>: | + | <b>[[Pipeline]]s</b>: 19 <b>[[Retire Station]]s</b>: 8 <b>[[Scratchpad]]</b>: 8192B |
<b>[[Spiller|Spill Buffers]]</b>: 8 <b>[[Spiller|Spiller Stack Size]]</b>: 16MB | <b>[[Spiller|Spill Buffers]]</b>: 8 <b>[[Spiller|Spiller Stack Size]]</b>: 16MB | ||
| − | <b>[[Memory#Instruction_Cache|iCache Line]]</b>: | + | <b>[[Memory#Instruction_Cache|iCache Line]]</b>: NoneB |
| − | <b>2 reader slots</b>, | + | <b>2 reader slots</b>, 17bits wide <b>2 writer slots</b>, 20bits wide <b>1 pick slots</b>, 11bits wide |
| − | <b>exu slot 0</b>, | + | <b>exu slot 0</b>, 19bits wide, with functional units: [[Functional Unit#alu|alu]] [[Functional Unit#count|count]] [[Functional Unit#mul|mul]] [[Functional Unit#NaR|NaR]] [[Functional Unit#nope|nope]] [[Functional Unit#shift|shift]] [[Functional Unit#shuffle|shuffle]] |
| − | <b>exu slot 1</b>, | + | <b>exu slot 1</b>, 7bits wide, with functional units: [[Functional Unit#cc|cc]] [[Functional Unit#exuArgs|exuArgs]] |
| − | <b>flow slot 0</b>, | + | <b>flow slot 0</b>, 18bits wide, with functional units: [[Functional Unit#boot|boot]] [[Functional Unit#cache|cache]] [[Functional Unit#con|con]] [[Functional Unit#conform|conform]] [[Functional Unit#control|control]] [[Functional Unit#ls|ls]] [[Functional Unit#misc|misc]] [[Functional Unit#nopf|nopf]] |
| − | <b>flow slot 1</b>, | + | <b>flow slot 1</b>, 8bits wide, with functional units: [[Functional Unit#flowArgs|flowArgs]] [[Functional Unit#nopf|nopf]] |
[[Cores/Copper/Encoding|Operation Encoding]] | [[Cores/Copper/Encoding|Operation Encoding]] | ||
Latest revision as of 14:15, 23 February 2021
The Copper core isn't much bigger than Tin, but here both flow and exu slots are properly populated with functional units, so instruction level parallelism is approximately doubled in comparison. Mobile devices, low power servers or smart devices like printers are the expected primary targets.
Belt: 8 Morsel: 3bit Scalar Width: 64bit Operand Maximum Size: 8B
Pipelines: 19 Retire Stations: 8 Scratchpad: 8192B
Spill Buffers: 8 Spiller Stack Size: 16MB
iCache Line: NoneB
2 reader slots, 17bits wide 2 writer slots, 20bits wide 1 pick slots, 11bits wide
exu slot 0, 19bits wide, with functional units: alu count mul NaR nope shift shuffle
exu slot 1, 7bits wide, with functional units: cc exuArgs
flow slot 0, 18bits wide, with functional units: boot cache con conform control ls misc nopf
flow slot 1, 8bits wide, with functional units: flowArgs nopf
