Difference between revisions of "Instruction Set/flip"

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{{DISPLAYTITLE:flip}}
 
{{DISPLAYTITLE:flip}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''aliases:''' flips flipu <br />
 
'''aliases:''' flips flipu <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
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<br />
 
<br />
  
 +
'''encoding:'''
 +
<code style="font-size:100%"><b style="color:#050">flip</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>)</code>
 +
<br />
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
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| [[Cores/Tin/Encoding#flip|Tin]] || E0 || 1
 
| [[Cores/Tin/Encoding#flip|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#flip|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#flip|Copper]] || E0 || 1
 
|-
 
|-
 
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 || 1
 
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#flip|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#flip|Gold]] || E0 || 1
−
|-
+
−
| [[Cores/Decimal8/Encoding#flip|Decimal8]] || E0 E1 E2 E3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#flip|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
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<br />
 
<br />
  
 +
'''encoding:'''
 +
<code style="font-size:100%"><b style="color:#050">flip</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>)</code>
 +
<br />
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#flip|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#flip|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#flip|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#flip|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 ||  
−
|-
+
−
| [[Cores/Gold/Encoding#flip|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
−
|-
+
−
| [[Cores/Decimal8/Encoding#flip|Decimal8]] || E0 E1 E2 E3 || 1
+
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#flip|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Gold/Encoding#flip|Gold]] || E0 ||  
 
|}
 
|}
  
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<br />
 
<br />
  
 +
'''encoding:'''
 +
<code style="font-size:100%"><b style="color:#050">flip</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>)</code>
 +
<br />
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#flip|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#flip|Tin]] || E0 ||  
−
|-
+
−
| [[Cores/Copper/Encoding#flip|Copper]] || E0 E1 || 1
+
−
|-
+
−
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 || 1
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#flip|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Copper/Encoding#flip|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#flip|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#flip|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#flip|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Gold/Encoding#flip|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:11, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

aliases: flips flipu
native on: all

Bit complement.

The dyadic operations change the single indexed bit.

related operations: set, clear, test

flip(op x) → op r0

operands: like Identity [xx:x]

Flips all bits, i.e. this is the bit complement.

encoding: flip(op x)

Core In Slots Latencies
Tin E0 1
Copper E0 1
Silver E0 E1 E2 E3 1
Gold E0 1

flip(op x, bit bit) → op r0

operands: like Shift [xi:x]


encoding: flip(op x)

Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

flip(op x, n bit) → op r0

operands: like Shift [xi:x]


encoding: flip(op x)

Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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