Difference between revisions of "Instruction Set/u2ffz"

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{{DISPLAYTITLE:u2ffz}}
 
{{DISPLAYTITLE:u2ffz}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br />
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
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'''native on:''' [[Cores/Silver|Silver]] <br />
 
</div>
 
</div>
  
convert unsigned integer to float
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Unsigned integer to binary float conversion. Rounding towards zero.
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----
 
<code style="font-size:130%"><b style="color:#050">u2ffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">u2ffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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|-
| [[Cores/Silver/Encoding#u2ffz|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
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| [[Cores/Silver/Encoding#u2ffz|Silver]] || E0 E1 || rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5  
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| [[Cores/Gold/Encoding#u2ffz|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
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|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:02, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   that produces condition codes and rounds toward zero

native on: Silver

Unsigned integer to binary float conversion. Rounding towards zero.




u2ffz(f x) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable