Difference between revisions of "Instruction Set/innerfln"

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enter a loop
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Enter predicated loop with multiple result values on false.
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Everything that applies to [[Instruction_Set/innern|innern]] applies also here. The difference is the predicate to make it a conditional inner. And there is one less possible argument in all the encodings.
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<b>related operations:</b>  [[Instruction_Set/innern|innern]], [[Instruction_Set/innerfln|innerfln]]
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<code style="font-size:130%"><b style="color:#050">innerfln</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="call argument from calls window">q</span>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">n</span></i>, <span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from  
 
<code style="font-size:130%"><b style="color:#050">innerfln</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="call argument from calls window">q</span>, <i><span style="color:#009">[[Immediates#lit|lit]]</span> <span title="morsel-sized manifest constant">n</span></i>, <span style="color:#009">[[Domains#p|p]]</span> <span title="call argument from  

Latest revision as of 17:49, 4 February 2015

realizing  flow stream  flow block  call phase   operation  

native on: all

Enter predicated loop with multiple result values on false.

Everything that applies to innern applies also here. The difference is the predicate to make it a conditional inner. And there is one less possible argument in all the encodings.

related operations: innern, innerfln


innerfln(op q, lit n, p target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innerfln(op q, lit n, p target, off argc, count args)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1

innerfln(op q, lit n, lbl target, args args) → ops r0 ...rn

operands: like Inv :


encoding: innerfln(op q, lit n, off target, count argc) , innerfln(op q, lit n, off target, count argc, lit argv)

Core In Slots Latencies
Tin F0 1
Copper F0 F1 1
Silver F0 F1 F2 1
Gold F0 F1 F2 F3 1
Decimal8 F0 F1 F2 1
Decimal16 F0 F1 F2 1


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