Difference between revisions of "Instruction Set/f2sfxn"

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{{DISPLAYTITLE:f2sfxn}}
 
{{DISPLAYTITLE:f2sfxn}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Overflow|using excepting overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Overflow|using excepting overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward negative infinity]]<br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
</div>
 
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Latest revision as of 09:31, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using excepting overflow behavior   that produces condition codes and rounds toward negative infinity

native on: Silver Gold

Inexactly convert a binary floating point value to a signed integer, rounding toward nearest and producing NaRs on overflow.


f2sfxn(f x) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Gold E0 E1 E2 E3 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable