Difference between revisions of "Instruction Set/andl"
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{{DISPLAYTITLE:andl}} | {{DISPLAYTITLE:andl}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the logical value domain]] [[Condition Code|that produces condition codes]]<br /> |
'''aliases:''' andls andlu <br /> | '''aliases:''' andls andlu <br /> | ||
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
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Bitwise and. | Bitwise and. | ||
| + | |||
| + | <b>related operations:</b> [[Instruction_Set/orl|orl]], [[Instruction_Set/flip|flip]], [[Instruction_Set/nand|nand]], [[Instruction_Set/nor|nor]], [[Instruction_Set/xorl|xorl]], [[Instruction_Set/nxor|nxor]], [[Instruction_Set/imp|imp]], [[Instruction_Set/nimp|nimp]] | ||
| + | |||
---- | ---- | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding#andl|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#andl|Tin]] || E0 || |
|- | |- | ||
| − | | [[Cores/Copper/Encoding#andl|Copper]] || E0 | + | | [[Cores/Copper/Encoding#andl|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/Silver/Encoding#andl|Silver]] || E0 E1 E2 E3 || | + | | [[Cores/Silver/Encoding#andl|Silver]] || E0 E1 E2 E3 || |
|- | |- | ||
| − | | [[Cores/Gold/Encoding#andl|Gold]] || E0 | + | | [[Cores/Gold/Encoding#andl|Gold]] || E0 || |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|} | |} | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding#andl|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#andl|Tin]] || E0 || |
| − | + | ||
| − | + | ||
| − | + | ||
| − | + | ||
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Copper/Encoding#andl|Copper]] || E0 || |
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Silver/Encoding#andl|Silver]] || E0 E1 E2 E3 || |
|- | |- | ||
| − | | [[Cores/ | + | | [[Cores/Gold/Encoding#andl|Gold]] || E0 || |
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:07, 23 February 2021
speculable exu stream exu block compute phase operation in the logical value domain that produces condition codes
aliases: andls andlu
native on: all
Bitwise and.
related operations: orl, flip, nand, nor, xorl, nxor, imp, nimp
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 E2 E3 | |
| Gold | E0 |
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | |
| Copper | E0 | |
| Silver | E0 E1 E2 E3 | |
| Gold | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
