Difference between revisions of "Instruction Set/adddz"
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{{DISPLAYTITLE:adddz}} | {{DISPLAYTITLE:adddz}} | ||
− | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br /> |
− | '''native on:''' [[ | + | '''native on:''' [[Assembly|none]]<br /> |
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 14:06, 23 February 2021
speculable exu stream exu block compute phase operation in the decimal floating point value domain that produces condition codes and rounds toward zero
native on: none
Decimal floating point add in current rounding towards zero.
operands: like Addd [dd:d]
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable