Difference between revisions of "Instruction Set/sub"

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{{DISPLAYTITLE:sub}}
 
{{DISPLAYTITLE:sub}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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'''aliases:''' subs subu subsv subuv <br />
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'''aliases:''' subs subu subs2 subu2 <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#sub|Tin]] || E0 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
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| [[Cores/Tin/Encoding#sub|Tin]] || E0 ||  
 
|-
 
|-
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| [[Cores/Copper/Encoding#sub|Copper]] || E0 E1 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
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| [[Cores/Copper/Encoding#sub|Copper]] || E0 ||  
 
|-
 
|-
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| [[Cores/Silver/Encoding#sub|Silver]] || E0 E1 E2 E3 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
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| [[Cores/Silver/Encoding#sub|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
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| [[Cores/Gold/Encoding#sub|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
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| [[Cores/Gold/Encoding#sub|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#sub|Decimal8]] || E0 E1 E2 E3 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
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−
|-
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−
| [[Cores/Decimal16/Encoding#sub|Decimal16]] || E0 E1 E2 E3 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#sub|Tin]] || E0 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
+
| [[Cores/Tin/Encoding#sub|Tin]] || E0 ||  
−
|-
+
−
| [[Cores/Copper/Encoding#sub|Copper]] || E0 E1 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
+
−
|-
+
−
| [[Cores/Silver/Encoding#sub|Silver]] || E0 E1 E2 E3 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
+
 
|-
 
|-
−
| [[Cores/Gold/Encoding#sub|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
+
| [[Cores/Copper/Encoding#sub|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#sub|Decimal8]] || E0 E1 E2 E3 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
+
| [[Cores/Silver/Encoding#sub|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#sub|Decimal16]] || E0 E1 E2 E3 || b,b:b=1 bv,bv:bv=1 h,h:h=1 hv,hv:hv=1 w,w:w=1 wv,wv:wv=1 d,d:d=2 dv,dv:dv=2 q,q:q=2 qv,qv:qv=2
+
| [[Cores/Gold/Encoding#sub|Gold]] || E0 ||  
 
|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:03, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain   that produces condition codes

aliases: subs subu subs2 subu2
native on: all

Normal unsigned substraction. Normal wraparound subtraction.

sub(op x, op y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

sub(op x, imm y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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