Difference between revisions of "Instruction Set/rrootu"

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{{DISPLAYTITLE:rrootu}}
 
{{DISPLAYTITLE:rrootu}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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|-
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| [[Cores/Tin/Encoding#rrootu|Tin]] || E0 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Tin/Encoding#rrootu|Tin]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
 
|-
 
|-
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| [[Cores/Copper/Encoding#rrootu|Copper]] || E0 E1 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Copper/Encoding#rrootu|Copper]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
 
|-
 
|-
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| [[Cores/Silver/Encoding#rrootu|Silver]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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| [[Cores/Silver/Encoding#rrootu|Silver]] || E0 E1 E2 E3 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
 
|-
 
|-
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| [[Cores/Gold/Encoding#rrootu|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
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| [[Cores/Gold/Encoding#rrootu|Gold]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2  
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|-
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| [[Cores/Decimal8/Encoding#rrootu|Decimal8]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2
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−
|-
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| [[Cores/Decimal16/Encoding#rrootu|Decimal16]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2  
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|}
 
|}
  
  
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 13:59, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the unsigned integer value domain   that produces condition codes

native on: all

reciprocal square root

rrootu(u x) → u r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2
Copper E0 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2
Silver E0 E1 E2 E3 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2
Gold E0 rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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