Difference between revisions of "Instruction Set/f2ufs"
From Mill Computing Wiki
| (2 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:f2ufs}} | {{DISPLAYTITLE:f2ufs}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Overflow|using saturating overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br /> |
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | '''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | ||
</div> | </div> | ||
Latest revision as of 09:24, 9 February 2015
speculable exu stream exu block compute phase operation in the binary floating point value domain using saturating overflow behavior that produces condition codes and rounds use current dynamic rounding mode
Inexactly convert a binary floating point value to a unsigned integer, in current rounding mode and producing saturating result values.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
