Difference between revisions of "Instruction Set/narrowfz"
From Mill Computing Wiki
| (3 intermediate revisions by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:narrowfz}} | {{DISPLAYTITLE:narrowfz}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] <br /> | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Rounding|and rounds toward zero]]<br /> |
| − | '''native on:''' [[Cores/Silver|Silver | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
| − | + | Half the width of a binary float value. Rounding towards zero. | |
| + | |||
| + | Can produce the [http://en.wikipedia.org/wiki/IEEE_floating_point IEEE 754] 16bit binary float interchange format. | ||
| + | |||
| + | This is not a [[Speculable]] operation. The reason for this is the impossibility to fit all of the [[NaR]] payload into values smaller than 32bit. | ||
| + | Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. | ||
| + | If narrowing should prove a big bottleneck this can be revisited. | ||
| + | |||
---- | ---- | ||
| − | <code style="font-size:130%"><b style="color:#050">narrowfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window"> | + | <code style="font-size:130%"><b style="color:#050">narrowfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v1</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v2</span>) → [[Domains#f|f]] r<sub>0</sub></code> |
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands# | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrowvf|like Narrowvf [FF:½F]]] |
</div> | </div> | ||
<br /> | <br /> | ||
| Line 14: | Line 21: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding#narrowfz|Silver]] || E0 E1 || | + | | [[Cores/Silver/Encoding#narrowfz|Silver]] || E0 E1 || |
| − | + | ||
| − | + | ||
|} | |} | ||
---- | ---- | ||
| − | <code style="font-size:130%"><b style="color:#050">narrowfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window"> | + | <code style="font-size:130%"><b style="color:#050">narrowfz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) → [[Domains#f|f]] r<sub>0</sub></code> |
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands# | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrowf|like Narrowf [ff:½f]]] |
</div> | </div> | ||
<br /> | <br /> | ||
| Line 28: | Line 33: | ||
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding#narrowfz|Silver]] || E0 E1 || | + | | [[Cores/Silver/Encoding#narrowfz|Silver]] || E0 E1 || |
| − | + | ||
| − | + | ||
|} | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 13:25, 23 February 2021
realizing exu stream exu block compute phase operation in the binary floating point value domain and rounds toward zero
native on: Silver
Half the width of a binary float value. Rounding towards zero.
Can produce the IEEE 754 16bit binary float interchange format.
This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.
operands: like Narrowvf [FF:½F]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 |
narrowfz(f op0, width width0) → f r0
operands: like Narrowf [ff:½f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
