Difference between revisions of "Instruction Set/andl"

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{{DISPLAYTITLE:andl}}
 
{{DISPLAYTITLE:andl}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
 
'''aliases:''' andls andlu <br />
 
'''aliases:''' andls andlu <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
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Bitwise and.
 
Bitwise and.
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<b>related operations:</b>  [[Instruction_Set/orl|orl]], [[Instruction_Set/flip|flip]], [[Instruction_Set/nand|nand]], [[Instruction_Set/nor|nor]], [[Instruction_Set/xorl|xorl]], [[Instruction_Set/nxor|nxor]], [[Instruction_Set/imp|imp]], [[Instruction_Set/nimp|nimp]]
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----
 
----
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Tin/Encoding#214|Tin]] || E0 || 1
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| [[Cores/Tin/Encoding#andl|Tin]] || E0 ||  
 
|-
 
|-
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| [[Cores/Copper/Encoding#214|Copper]] || E0 E1 || 1
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| [[Cores/Copper/Encoding#andl|Copper]] || E0 ||  
 
|-
 
|-
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| [[Cores/Silver/Encoding#214|Silver]] || E0 E1 E2 E3 || 1
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| [[Cores/Silver/Encoding#andl|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
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| [[Cores/Gold/Encoding#214|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
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| [[Cores/Gold/Encoding#andl|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#214|Decimal8]] || E0 E1 E2 E3 || 1
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−
|-
+
−
| [[Cores/Decimal16/Encoding#214|Decimal16]] || E0 E1 E2 E3 || 1
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|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#213|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#andl|Tin]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Copper/Encoding#213|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#andl|Copper]] || E0 ||  
 
|-
 
|-
−
| [[Cores/Silver/Encoding#213|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#andl|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
−
| [[Cores/Gold/Encoding#213|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
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| [[Cores/Gold/Encoding#andl|Gold]] || E0 ||  
−
|-
+
−
| [[Cores/Decimal8/Encoding#213|Decimal8]] || E0 E1 E2 E3 || 1
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#213|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
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 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:07, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain   that produces condition codes

aliases: andls andlu
native on: all

Bitwise and.

related operations: orl, flip, nand, nor, xorl, nxor, imp, nimp


andl(op x, op y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

andl(op x, imm y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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