Difference between revisions of "Instruction Set/rootfe"
From Mill Computing Wiki
(5 intermediate revisions by the same user not shown) | |||
Line 1: | Line 1: | ||
{{DISPLAYTITLE:rootfe}} | {{DISPLAYTITLE:rootfe}} | ||
− | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties toward even adjacent value]]<br /> |
− | '''native on:''' [[ | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
− | Floating point square root | + | Floating point square root rounding towards even. |
---- | ---- | ||
Line 11: | Line 11: | ||
</div> | </div> | ||
<br /> | <br /> | ||
+ | |||
+ | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
+ | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
+ | |- | ||
+ | | [[Cores/Silver/Encoding#rootfe|Silver]] || E0 || rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5 | ||
+ | |} | ||
+ | |||
+ | |||
+ | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 14:06, 23 February 2021
speculable exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes and rounds to nearest, ties toward even adjacent value
native on: Silver
Floating point square root rounding towards even.
operands: like Addf [ff:f]
Core | In Slots | Latencies |
---|---|---|
Silver | E0 | rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable