Difference between revisions of "Instruction Set/addffz"
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{{DISPLAYTITLE:addffz}} | {{DISPLAYTITLE:addffz}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties away from zero]]<br /> |
| − | '''native on:''' [[Cores/Silver|Silver | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
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| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#addffz|Silver]] || E0 E1 || |
| − | + | ||
| − | + | ||
|} | |} | ||
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| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:02, 23 February 2021
speculable exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes and rounds to nearest, ties away from zero
native on: Silver
Floating point add in current rounding away from zero.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
