Difference between revisions of "Instruction Set/subdfz"

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{{DISPLAYTITLE:subdfz}}
 
{{DISPLAYTITLE:subdfz}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties away from zero]]<br />
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'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
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'''native on:''' [[Assembly|none]]<br />
 
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
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|-
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| [[Cores/Decimal8/Encoding#851|Decimal8]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
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|-
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| [[Cores/Decimal16/Encoding#851|Decimal16]] || E0 E1 || d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
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|}
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Latest revision as of 14:03, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   that produces condition codes and rounds to nearest, ties away from zero

native on: none

Decimal floating point subtraction in current rounding away from zero.

subdfz(d x, d y) → d r0

operands: like Addd [dd:d]



Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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