Difference between revisions of "Instruction Set/f2uf"

From Mill Computing Wiki
Jump to: navigation, search
 
(3 intermediate revisions by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:f2uf}}
 
{{DISPLAYTITLE:f2uf}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Overflow|using modulo overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Overflow|using modulo overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds use current dynamic rounding mode]]<br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
 
</div>
 
</div>
Line 15:Line 15:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Silver/Encoding#423|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
+
| [[Cores/Silver/Encoding#f2uf|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|-
 
|-
| [[Cores/Gold/Encoding#423|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
+
| [[Cores/Gold/Encoding#f2uf|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:27, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   using modulo overflow behavior   that produces condition codes and rounds use current dynamic rounding mode

native on: Silver Gold

Inexactly convert a binary floating point value to a unsigned integer, in current rounding mode and normal modulo overflow.


f2uf(f x) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Gold E0 E1 E2 E3 w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable