Difference between revisions of "Instruction Set/f2sedxfz"

From Mill Computing Wiki
Jump to: navigation, search
 
(3 intermediate revisions by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:f2sedxfz}}
 
{{DISPLAYTITLE:f2sedxfz}}
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Overflow|using excepting overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the decimal floating point value domain]]&nbsp;&nbsp; [[Overflow|using excepting overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties away from zero]]<br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br />
 
</div>
 
</div>
Line 15:Line 15:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#328|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
+
| [[Cores/Decimal8/Encoding#f2sedxfz|Decimal8]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#328|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
+
| [[Cores/Decimal16/Encoding#f2sedxfz|Decimal16]] || E0 E1 || d:d=4 dv:dv=4 q:q=5 qv:qv=5  
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 09:26, 9 February 2015

speculable  exu stream  exu block  compute phase   operation   in the decimal floating point value domain   using excepting overflow behavior   that produces condition codes and rounds to nearest, ties away from zero

native on: Decimal8 Decimal16

Exactly convert a decimal floating point value to a signed integer, rounding away from zero and producing NaRs on overflow.

f2sedxfz(d x) → d r0

operands: like Addd [dd:d]


Core In Slots Latencies
Decimal8 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5
Decimal16 E0 E1 d:d=4 dv:dv=4 q:q=5 qv:qv=5


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

Retrieved from "http://millcomputing.com/w/index.php?title=Instruction_Set/f2sedxfz&oldid=3780"