Difference between revisions of "Cores/Copper"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:Copper Core}} <b>Cores:</b> Tin Copper Silver Gold Cores/Decimal8|Decim...")
 
 
(4 intermediate revisions by 2 users not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:Copper Core}}
 
{{DISPLAYTITLE:Copper Core}}
−
<b>[[Cores]]:</b> [[Cores/Tin|Tin]]&nbsp;[[Cores/Copper|Copper]]&nbsp;[[Cores/Silver|Silver]]&nbsp;[[Cores/Gold|Gold]]&nbsp;[[Cores/Decimal8|Decimal8]]&nbsp;[[Cores/Decimal16|Decimal16]]&nbsp;
+
<b>[[Cores]]:</b> [[Cores/Tin|Tin]]&nbsp;[[Cores/Copper|Copper]]&nbsp;[[Cores/Silver|Silver]]&nbsp;[[Cores/Gold|Gold]]&nbsp;
  
−
The Copper core isn't muh bigger than Tin, but here both flow and exu slots are properly populated with functional units, so instruction level parallelism is approximately doubled in comparison. Mobile devices, low power servers or smart devices like printers are the expected primary targets.
+
The Copper core isn't much bigger than Tin, but here both flow and exu slots are properly populated with functional units, so instruction level parallelism is approximately doubled in comparison. Mobile devices, low power servers or smart devices like printers are the expected primary targets.
  
  
 
<b>[[Belt]]</b>: 8&nbsp;&nbsp;<b>[[Decode#Morsel|Morsel]]</b>: 3bit&nbsp;&nbsp;<b>[[Operands|Scalar Width]]</b>: 64bit&nbsp;&nbsp;<b>[[Operands|Operand Maximum Size]]</b>: 8B&nbsp;&nbsp;
 
<b>[[Belt]]</b>: 8&nbsp;&nbsp;<b>[[Decode#Morsel|Morsel]]</b>: 3bit&nbsp;&nbsp;<b>[[Operands|Scalar Width]]</b>: 64bit&nbsp;&nbsp;<b>[[Operands|Operand Maximum Size]]</b>: 8B&nbsp;&nbsp;
  
−
<b>[[Pipeline]]s</b>: 13&nbsp;&nbsp;<b>[[Retire Station]]s</b>: 8&nbsp;&nbsp;<b>[[Scratchpad]]</b>: 128B&nbsp;&nbsp;
+
<b>[[Pipeline]]s</b>: 19&nbsp;&nbsp;<b>[[Retire Station]]s</b>: 8&nbsp;&nbsp;<b>[[Scratchpad]]</b>: 8192B&nbsp;&nbsp;
  
 
<b>[[Spiller|Spill Buffers]]</b>: 8&nbsp;&nbsp;<b>[[Spiller|Spiller Stack Size]]</b>: 16MB&nbsp;&nbsp;
 
<b>[[Spiller|Spill Buffers]]</b>: 8&nbsp;&nbsp;<b>[[Spiller|Spiller Stack Size]]</b>: 16MB&nbsp;&nbsp;
  
−
<b>[[Memory#Instruction_Cache|iCache Line]]</b>: 16B&nbsp;&nbsp;
+
<b>[[Memory#Instruction_Cache|iCache Line]]</b>: NoneB&nbsp;&nbsp;
  
−
<b>2 reader slots</b>, 9bits wide&nbsp;&nbsp;&nbsp;<b>2 writer slots</b>, 6bits wide&nbsp;&nbsp;&nbsp;<b>1 pick slots</b>, 10bits wide&nbsp;&nbsp;&nbsp;
+
<b>2 reader slots</b>, 17bits wide&nbsp;&nbsp;&nbsp;<b>2 writer slots</b>, 20bits wide&nbsp;&nbsp;&nbsp;<b>1 pick slots</b>, 11bits wide&nbsp;&nbsp;&nbsp;
  
−
<b>exu slot 0</b>, 18bits wide, with functional units: [[Functional Unit#alu|alu]]&nbsp;[[Functional Unit#count|count]]&nbsp;[[Functional Unit#mul|mul]]&nbsp;[[Functional Unit#nope|nope]]&nbsp;[[Functional Unit#shift|shift]]&nbsp;[[Functional Unit#shuffle|shuffle]]&nbsp;
+
<b>exu slot 0</b>, 19bits wide, with functional units: [[Functional Unit#alu|alu]]&nbsp;[[Functional Unit#count|count]]&nbsp;[[Functional Unit#mul|mul]]&nbsp;[[Functional Unit#NaR|NaR]]&nbsp;[[Functional Unit#nope|nope]]&nbsp;[[Functional Unit#shift|shift]]&nbsp;[[Functional Unit#shuffle|shuffle]]&nbsp;
  
−
<b>exu slot 1</b>, 16bits wide, with functional units: [[Functional Unit#alu|alu]]&nbsp;[[Functional Unit#exuArgs|exuArgs]]&nbsp;
+
<b>exu slot 1</b>, 7bits wide, with functional units: [[Functional Unit#cc|cc]]&nbsp;[[Functional Unit#exuArgs|exuArgs]]&nbsp;
  
−
<b>flow slot 0</b>, 15bits wide, with functional units: [[Functional Unit#cache|cache]]&nbsp;[[Functional Unit#con|con]]&nbsp;[[Functional Unit#conform|conform]]&nbsp;[[Functional Unit#control|control]]&nbsp;[[Functional Unit#ls|ls]]&nbsp;[[Functional Unit#misc|misc]]&nbsp;[[Functional Unit#nopf|nopf]]&nbsp;
+
<b>flow slot 0</b>, 18bits wide, with functional units: [[Functional Unit#boot|boot]]&nbsp;[[Functional Unit#cache|cache]]&nbsp;[[Functional Unit#con|con]]&nbsp;[[Functional Unit#conform|conform]]&nbsp;[[Functional Unit#control|control]]&nbsp;[[Functional Unit#ls|ls]]&nbsp;[[Functional Unit#misc|misc]]&nbsp;[[Functional Unit#nopf|nopf]]&nbsp;
  
−
<b>flow slot 1</b>, 15bits wide, with functional units: [[Functional Unit#con|con]]&nbsp;[[Functional Unit#conform|conform]]&nbsp;[[Functional Unit#control|control]]&nbsp;[[Functional Unit#flowArgs|flowArgs]]&nbsp;[[Functional Unit#ls|ls]]&nbsp;
+
<b>flow slot 1</b>, 8bits wide, with functional units: [[Functional Unit#flowArgs|flowArgs]]&nbsp;[[Functional Unit#nopf|nopf]]&nbsp;
  
  
  
 
[[Cores/Copper/Encoding|Operation Encoding]]
 
[[Cores/Copper/Encoding|Operation Encoding]]

Latest revision as of 14:15, 23 February 2021

Cores: Tin Copper Silver Gold 

The Copper core isn't much bigger than Tin, but here both flow and exu slots are properly populated with functional units, so instruction level parallelism is approximately doubled in comparison. Mobile devices, low power servers or smart devices like printers are the expected primary targets.


Belt: 8  Morsel: 3bit  Scalar Width: 64bit  Operand Maximum Size: 8B  

Pipelines: 19  Retire Stations: 8  Scratchpad: 8192B  

Spill Buffers: 8  Spiller Stack Size: 16MB  

iCache Line: NoneB  

2 reader slots, 17bits wide   2 writer slots, 20bits wide   1 pick slots, 11bits wide   

exu slot 0, 19bits wide, with functional units: alu count mul NaR nope shift shuffle 

exu slot 1, 7bits wide, with functional units: cc exuArgs 

flow slot 0, 18bits wide, with functional units: boot cache con conform control ls misc nopf 

flow slot 1, 8bits wide, with functional units: flowArgs nopf 


Operation Encoding

Retrieved from "http://millcomputing.com/w/index.php?title=Cores/Copper&oldid=5543"