Difference between revisions of "Instruction Set/nor"

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{{DISPLAYTITLE:nor}}
 
{{DISPLAYTITLE:nor}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''aliases:''' nors noru <br />
 
'''aliases:''' nors noru <br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
  
bitwise complement of inclusive or
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Bitwise nor.
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<b>related operations:</b>  [[Instruction_Set/andl|andl]], [[Instruction_Set/orl|orl]], [[Instruction_Set/flip|flip]], [[Instruction_Set/nand|nand]], [[Instruction_Set/xorl|xorl]], [[Instruction_Set/nxor|nxor]], [[Instruction_Set/imp|imp]], [[Instruction_Set/nimp|nimp]]
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">nor</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">nor</b>(<span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#696|Tin]] || E0 || 1
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| [[Cores/Tin/Encoding#nor|Tin]] || E0 ||  
 
|-
 
|-
| [[Cores/Copper/Encoding#696|Copper]] || E0 E1 || 1
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| [[Cores/Copper/Encoding#nor|Copper]] || E0 ||  
 
|-
 
|-
| [[Cores/Silver/Encoding#696|Silver]] || E0 E1 E2 E3 || 1
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| [[Cores/Silver/Encoding#nor|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
| [[Cores/Gold/Encoding#696|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#nor|Gold]] || E0 ||  
|-
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| [[Cores/Decimal8/Encoding#696|Decimal8]] || E0 E1 E2 E3 || 1
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|-
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| [[Cores/Decimal16/Encoding#696|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
| [[Cores/Tin/Encoding#697|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#nor|Tin]] || E0 ||  
 
|-
 
|-
| [[Cores/Copper/Encoding#697|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#nor|Copper]] || E0 ||  
 
|-
 
|-
| [[Cores/Silver/Encoding#697|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#nor|Silver]] || E0 E1 E2 E3 ||  
 
|-
 
|-
| [[Cores/Gold/Encoding#697|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#nor|Gold]] || E0 ||  
|-
+
| [[Cores/Decimal8/Encoding#697|Decimal8]] || E0 E1 E2 E3 || 1
+
|-
+
| [[Cores/Decimal16/Encoding#697|Decimal16]] || E0 E1 E2 E3 || 1
+
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:12, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the logical value domain  

aliases: nors noru
native on: all

Bitwise nor.

related operations: andl, orl, flip, nand, xorl, nxor, imp, nimp


nor(op x, op y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0

nor(op x, imm y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0
Copper E0
Silver E0 E1 E2 E3
Gold E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable