Difference between revisions of "Instruction Set/f2sfn"
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(Created page with "{{DISPLAYTITLE:f2sfn}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream [[Decode|exu block]...") | |||
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{{DISPLAYTITLE:f2sfn}} | {{DISPLAYTITLE:f2sfn}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Overflow|using modulo overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward negative infinity]]<br /> |
'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | '''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br /> | ||
</div> | </div> | ||
| − | convert | + | Inexactly convert a binary floating point value to a signed integer, rounding toward nearest and normal modulo overflow. |
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">f2sfn</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">f2sfn</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#f2sfn|Silver]] || E0 E1 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#f2sfn|Gold]] || E0 E1 E2 E3 || w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
|} | |} | ||
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| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 09:33, 9 February 2015
speculable exu stream exu block compute phase operation in the binary floating point value domain using modulo overflow behavior that produces condition codes and rounds toward negative infinity
Inexactly convert a binary floating point value to a signed integer, rounding toward nearest and normal modulo overflow.
operands: like Addf [ff:f]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 E1 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Gold | E0 E1 E2 E3 | w:w=3 wv:wv=3 d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
