Difference between revisions of "Instruction Set/addfz"

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{{DISPLAYTITLE:addfz}}
 
{{DISPLAYTITLE:addfz}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br />
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'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
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'''native on:''' [[Cores/Silver|Silver]] <br />
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
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| [[Cores/Silver/Encoding#addfz|Silver]] || E0 E1 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
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| [[Cores/Silver/Encoding#addfz|Silver]] || E0 E1 ||  
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|-
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| [[Cores/Gold/Encoding#addfz|Gold]] || E0 E1 E2 E3 || w,w:w=3 wv,wv:wv=3 d,d:d=4 dv,dv:dv=4 q,q:q=5 qv,qv:qv=5
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|}
 
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
 
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:14, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   that produces condition codes and rounds toward zero

native on: Silver

Floating point add in current rounding towards zero.

addfz(f x, f y) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0 E1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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