Difference between revisions of "Instruction Set/rroots"
From Mill Computing Wiki
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{{DISPLAYTITLE:rroots}} | {{DISPLAYTITLE:rroots}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed integer value domain]] <br /> | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the signed integer value domain]] [[Condition Code|that produces condition codes]]<br /> |
'''native on:''' [[Cores|all]]<br /> | '''native on:''' [[Cores|all]]<br /> | ||
</div> | </div> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding#rroots|Tin]] || E0 || | + | | [[Cores/Tin/Encoding#rroots|Tin]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding#rroots|Copper]] || E0 | + | | [[Cores/Copper/Encoding#rroots|Copper]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding#rroots|Silver]] || E0 E1 E2 E3 || | + | | [[Cores/Silver/Encoding#rroots|Silver]] || E0 E1 E2 E3 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
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| − | | [[Cores/Gold/Encoding#rroots|Gold]] || E0 | + | | [[Cores/Gold/Encoding#rroots|Gold]] || E0 || rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:13, 23 February 2021
speculable exu stream exu block compute phase operation in the signed integer value domain that produces condition codes
native on: all
reciprocal square root
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
| Copper | E0 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
| Silver | E0 E1 E2 E3 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
| Gold | E0 | rb:rb=1 rh:rh=1 rw:rw=1 rd:rd=2 rq:rq=2 rvb:rvb=1 rvh:rvh=1 rvw:rvw=1 rvd:rvd=2 rvq:rvq=2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
