Difference between revisions of "Instruction Set/wr"

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(Created page with "{{DISPLAYTITLE:wr}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|writer block]...")
 
 
(3 intermediate revisions by the same user not shown)
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{{DISPLAYTITLE:wr}}
 
{{DISPLAYTITLE:wr}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|writer block]]&nbsp;&nbsp;[[Phasing|writer phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|writer block]]&nbsp;&nbsp;[[Phasing|writer phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>
Line 6:Line 6:
 
hardware writer
 
hardware writer
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">wr</b>(<span style="color:#009">[[Sources#scratch|scratch]]</span> <span title="scratchpad byte number">dst</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="value written">v</span>)</code>
+
<code style="font-size:130%"><b style="color:#050">wr</b>(<span style="color:#009">[[Sources#reg|reg]]</span> <span title="special register name (as used in a Writer)">dst</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="value written">v</span>)</code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
 
</div>
 
</div>
Line 14:Line 14:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#912|Tin]] || W0 W1 || 3
+
| [[Cores/Tin/Encoding#wr|Tin]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Copper/Encoding#912|Copper]] || W0 W1 || 3
+
| [[Cores/Copper/Encoding#wr|Copper]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Silver/Encoding#912|Silver]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Silver/Encoding#wr|Silver]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#912|Gold]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Gold/Encoding#wr|Gold]] || W0 W1 || 3
−
|-
+
−
| [[Cores/Decimal8/Encoding#912|Decimal8]] || W0 W1 W2 W3 W4 || 3
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#912|Decimal16]] || W0 W1 W2 W3 W4 || 3
+
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">wr</b>(<span style="color:#009">[[Sources#reg|reg]]</span> <span title="special register name (as used in a Writer)">dst</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="value written">v</span>)</code>
+
<code style="font-size:130%"><b style="color:#050">wr</b>(<span style="color:#009">[[Sources#stream|stream]]</span> <span title="streamer number (as used in a Writer)">dst</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="value written">v</span>)</code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
 
</div>
 
</div>
Line 36:Line 32:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#913|Tin]] || W0 W1 || 3
+
| [[Cores/Tin/Encoding#wr|Tin]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Copper/Encoding#913|Copper]] || W0 W1 || 3
+
| [[Cores/Copper/Encoding#wr|Copper]] || W0 W1 || 3
 
|-
 
|-
−
| [[Cores/Silver/Encoding#913|Silver]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Silver/Encoding#wr|Silver]] || W0 W1 W2 W3 W4 || 3
 
|-
 
|-
−
| [[Cores/Gold/Encoding#913|Gold]] || W0 W1 W2 W3 W4 || 3
+
| [[Cores/Gold/Encoding#wr|Gold]] || W0 W1 || 3
−
|-
+
−
| [[Cores/Decimal8/Encoding#913|Decimal8]] || W0 W1 W2 W3 W4 || 3
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#913|Decimal16]] || W0 W1 W2 W3 W4 || 3
+
 
|}
 
|}
  
−
----
 
−
<code style="font-size:130%"><b style="color:#050">wr</b>(<span style="color:#009">[[Sources#stream|stream]]</span> <span title="streamer number (as used in a Writer)">dst</span>, <span style="color:#009">[[Domains#op|op]]</span> <span title="value written">v</span>)</code>
 
−
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNoResult|like NoResult [xx]:]]
 
−
</div>
 
−
<br />
 
  
−
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
+
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]
−
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
+
−
|-
+
−
| [[Cores/Tin/Encoding#914|Tin]] || W0 W1 || 3
+
−
|-
+
−
| [[Cores/Copper/Encoding#914|Copper]] || W0 W1 || 3
+
−
|-
+
−
| [[Cores/Silver/Encoding#914|Silver]] || W0 W1 W2 W3 W4 || 3
+
−
|-
+
−
| [[Cores/Gold/Encoding#914|Gold]] || W0 W1 W2 W3 W4 || 3
+
−
|-
+
−
| [[Cores/Decimal8/Encoding#914|Decimal8]] || W0 W1 W2 W3 W4 || 3
+
−
|-
+
−
| [[Cores/Decimal16/Encoding#914|Decimal16]] || W0 W1 W2 W3 W4 || 3
+
−
|}
+

Latest revision as of 14:12, 23 February 2021

speculable  exu stream  writer block  writer phase   operation   in the logical value domain  

native on: all

hardware writer

wr(reg dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 3

wr(stream dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 3


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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