Difference between revisions of "Instruction Set/remu"
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{{DISPLAYTITLE:remu}} | {{DISPLAYTITLE:remu}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the unsigned integer value domain]] [[Condition Code|that produces condition codes]]<br /> |
| − | '''native on:''' [[ | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
| − | + | Unsigned integer modulo for remainder. | |
| + | |||
| + | <b>related operations:</b> [[Instruction_Set/divu|divu]], [[Instruction_Set/divRemu|divRemu]], [[Instruction_Set/rdivu|rdivu]], [[Instruction_Set/rootu|rootu]], [[Instruction_Set/rrootu|rrootu]] | ||
| + | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">remu</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#u|u]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">remu</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">y</span>) → [[Domains#u|u]] r<sub>0</sub></code> | ||
| Line 10: | Line 13: | ||
</div> | </div> | ||
<br /> | <br /> | ||
| + | |||
| + | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
| + | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
| + | |- | ||
| + | | [[Cores/Silver/Encoding#remu|Silver]] || E0 || | ||
| + | |} | ||
---- | ---- | ||
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</div> | </div> | ||
<br /> | <br /> | ||
| + | |||
| + | {| class="mw-collapsible mw-collapsed wikitable" data-expandtext="▸" data-collapsetext="▾" | ||
| + | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
| + | |- | ||
| + | | [[Cores/Silver/Encoding#remu|Silver]] || E0 || | ||
| + | |} | ||
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Latest revision as of 14:09, 23 February 2021
speculable exu stream exu block compute phase operation in the unsigned integer value domain that produces condition codes
native on: Silver
Unsigned integer modulo for remainder.
related operations: divu, divRemu, rdivu, rootu, rrootu
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 |
operands: like Identity [xx:x]
| Core | In Slots | Latencies |
|---|---|---|
| Silver | E0 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
