Difference between revisions of "Instruction Set/narrowffz"

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(Created page with "{{DISPLAYTITLE:narrowffz}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream Decode|exu bl...")
 
 
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{{DISPLAYTITLE:narrowffz}}
 
{{DISPLAYTITLE:narrowffz}}
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Rounding|and rounds to nearest, ties away from zero]]<br />
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'''native on:''' [[Cores/Silver|Silver]] [[Cores/Gold|Gold]] <br />
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'''native on:''' [[Cores/Silver|Silver]] <br />
 
</div>
 
</div>
  
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narrow scalar to half width
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Half the width of a binary float value. Rounding to nearest away from zero.
 +
 
 +
Can produce the [http://en.wikipedia.org/wiki/IEEE_floating_point IEEE 754] 16bit binary float interchange format.
 +
 
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This is not a [[Speculable]] operation. The reason for this is the impossibility to fit all of the [[NaR]] payload into values smaller than 32bit.
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Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so.
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If narrowing should prove a big bottleneck this can be revisited.
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<code style="font-size:130%"><b style="color:#050">narrowffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
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<code style="font-size:130%"><b style="color:#050">narrowffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v1</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v2</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrowf|like Narrowf [ff:&#189;f]]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrowvf|like Narrowvf [FF:&#189;F]]]
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Silver/Encoding#658|Silver]] || E0 E1 || w:h=3 d:w=4 q:d=5
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| [[Cores/Silver/Encoding#narrowffz|Silver]] || E0 E1 ||  
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|-
+
−
| [[Cores/Gold/Encoding#658|Gold]] || E0 E1 E2 E3 || w:h=3 d:w=4 q:d=5
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|}
 
|}
  
 
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----
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<code style="font-size:130%"><b style="color:#050">narrowffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v1</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">v2</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
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<code style="font-size:130%"><b style="color:#050">narrowffz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">op0</span>, <i><span style="color:#009">[[Immediates#width|width]]</span> <span title="data width and vector length (exu)">width0</span></i>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrowvf|like Narrowvf [FF:&#189;F]]]
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeNarrowf|like Narrowf [ff:&#189;f]]]
 
</div>
 
</div>
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
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| [[Cores/Silver/Encoding#657|Silver]] || E0 E1 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5
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| [[Cores/Silver/Encoding#narrowffz|Silver]] || E0 E1 ||  
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|-
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−
| [[Cores/Gold/Encoding#657|Gold]] || E0 E1 E2 E3 || wv,wv:hv=3 dv,dv:wv=4 qv,qv:dv=5
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|}
 
|}
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[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:06, 23 February 2021

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain   and rounds to nearest, ties away from zero

native on: Silver

Half the width of a binary float value. Rounding to nearest away from zero.

Can produce the IEEE 754 16bit binary float interchange format.

This is not a Speculable operation. The reason for this is the impossibility to fit all of the NaR payload into values smaller than 32bit. Nominally this would only require the narrowing of 32bit values to be not speculable, but for simplicity reasons in hardware and compiler this is not so. If narrowing should prove a big bottleneck this can be revisited.

narrowffz(f v1, f v2) → f r0

operands: like Narrowvf [FF:½F]


Core In Slots Latencies
Silver E0 E1

narrowffz(f op0, width width0) → f r0

operands: like Narrowf [ff:½f]


Core In Slots Latencies
Silver E0 E1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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