Difference between revisions of "Instruction Set/divfn"

From Mill Computing Wiki
Jump to: navigation, search
(Created page with "{{DISPLAYTITLE:divfn}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream [[Decode|exu block]...")
 
 
(5 intermediate revisions by the same user not shown)
Line 1:Line 1:
 
{{DISPLAYTITLE:divfn}}
 
{{DISPLAYTITLE:divfn}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]]<br />
+
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward negative infinity]]<br />
'''native on:''' [[Assembly|none]]<br />
+
'''native on:''' [[Cores/Silver|Silver]] <br />
 
</div>
 
</div>
  
divide for quotient
+
Floating point division in current rounding to nearest.
 +
 
 
----
 
----
 
<code style="font-size:130%"><b style="color:#050">divfn</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
 
<code style="font-size:130%"><b style="color:#050">divfn</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>, <span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">y</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
Line 10:Line 11:
 
</div>
 
</div>
 
<br />
 
<br />
 +
 +
{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
 +
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 +
|-
 +
| [[Cores/Silver/Encoding#divfn|Silver]] || E0 ||
 +
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Latest revision as of 14:04, 23 February 2021

speculable  exu stream  exu block  compute phase   operation   in the binary floating point value domain   that produces condition codes and rounds toward negative infinity

native on: Silver

Floating point division in current rounding to nearest.


divfn(f x, f y) → f r0

operands: like Addf [ff:f]


Core In Slots Latencies
Silver E0


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable