Difference between revisions of "Instruction Set/negf"
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{{DISPLAYTITLE:negf}} | {{DISPLAYTITLE:negf}} | ||
− | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the binary floating point value domain]] [[Condition Code|that produces condition codes]]<br /> |
− | '''native on:''' [[Cores/Silver|Silver | + | '''native on:''' [[Cores/Silver|Silver]] <br /> |
</div> | </div> | ||
− | + | Binary float arithmetic negation. | |
+ | |||
---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">negf</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">negf</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">x</span>) → [[Domains#f|f]] r<sub>0</sub></code> | ||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#negf|Silver]] || E0 E1 || rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5 |
− | + | ||
− | + | ||
|} | |} | ||
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+ | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Latest revision as of 14:04, 23 February 2021
speculable exu stream exu block compute phase operation in the binary floating point value domain that produces condition codes
native on: Silver
Binary float arithmetic negation.
operands: like Addf [ff:f]
Core | In Slots | Latencies |
---|---|---|
Silver | E0 E1 | rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable