Difference between revisions of "Instruction Set/wr"

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m (Protected "Instruction Set/wr": generated ([Edit=<protect-level-bot>] (indefinite) [Move=<protect-level-bot>] (indefinite)))
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{{DISPLAYTITLE:wr}}
 
{{DISPLAYTITLE:wr}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|writer block]]&nbsp;&nbsp;[[Phasing|writer phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
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<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|writer block]]&nbsp;&nbsp;[[Phasing|writer phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the logical value domain]]&nbsp;&nbsp;<br />
 
'''native on:''' [[Cores|all]]<br />
 
'''native on:''' [[Cores|all]]<br />
 
</div>
 
</div>

Revision as of 09:33, 9 February 2015

speculable  exu stream  writer block  writer phase   operation   in the logical value domain  

native on: all

hardware writer


wr(scratch dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 W2 W3 W4 3
Decimal8 W0 W1 W2 W3 W4 3
Decimal16 W0 W1 W2 W3 W4 3

wr(reg dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 W2 W3 W4 3
Decimal8 W0 W1 W2 W3 W4 3
Decimal16 W0 W1 W2 W3 W4 3

wr(stream dst, op v)

operands: like NoResult [xx]:


Core In Slots Latencies
Tin W0 W1 3
Copper W0 W1 3
Silver W0 W1 W2 W3 W4 3
Gold W0 W1 W2 W3 W4 3
Decimal8 W0 W1 W2 W3 W4 3
Decimal16 W0 W1 W2 W3 W4 3


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable