Difference between revisions of "Instruction Set/f2sedn"
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{{DISPLAYTITLE:f2sedn}} | {{DISPLAYTITLE:f2sedn}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Overflow|using modulo overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward negative infinity]]<br /> |
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | '''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | ||
</div> | </div> | ||
Latest revision as of 09:30, 9 February 2015
speculable exu stream exu block compute phase operation in the decimal floating point value domain using modulo overflow behavior that produces condition codes and rounds toward negative infinity
Exactly convert a decimal floating point value to a signed integer, rounding toward nearest and normal modulo overflow.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
