Difference between revisions of "Instruction Set/f2udxe"
From Mill Computing Wiki
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
{{DISPLAYTITLE:f2udxe}} | {{DISPLAYTITLE:f2udxe}} | ||
| − | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation| | + | <div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]] [[Encoding|exu stream]] [[Decode|exu block]] [[Phasing|compute phase]] operation [[Domains|in the decimal floating point value domain]] [[Overflow|using excepting overflow behavior]] [[Condition Code|that produces condition codes]] [[Rounding|and rounds to nearest, ties toward even adjacent value]]<br /> |
'''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | '''native on:''' [[Cores/Decimal8|Decimal8]] [[Cores/Decimal16|Decimal16]] <br /> | ||
</div> | </div> | ||
Latest revision as of 09:23, 9 February 2015
speculable exu stream exu block compute phase operation in the decimal floating point value domain using excepting overflow behavior that produces condition codes and rounds to nearest, ties toward even adjacent value
Inexactly convert a decimal floating point value to a unsigned integer, rounding toward even and producing NaRs on overflow.
operands: like Addd [dd:d]
| Core | In Slots | Latencies |
|---|---|---|
| Decimal8 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
| Decimal16 | E0 E1 | d:d=4 dv:dv=4 q:q=5 qv:qv=5 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
