Difference between revisions of "Instruction Set/widens"
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| − | + | Double the scalar width of a signed integer. | |
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| + | Sign extends the upper half. | ||
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| + | The natively available byte widths on all [[Cores]] are 1, 2, 4, 8, and on the high end also 16. | ||
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---- | ---- | ||
<code style="font-size:130%"><b style="color:#050">widens</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#s|s]] r<sub>0</sub></code> | <code style="font-size:130%"><b style="color:#050">widens</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">v</span>) → [[Domains#s|s]] r<sub>0</sub></code> | ||
Revision as of 10:40, 11 January 2015
realizing exu stream exu block compute phase operation in the signed integer value domain
native on: all
Double the scalar width of a signed integer.
Sign extends the upper half.
The natively available byte widths on all Cores are 1, 2, 4, 8, and on the high end also 16.
operands: like Widen xx:2x
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | b:h=1 h:w=1 w:d=2 d:q=2 |
| Copper | E0 E1 | b:h=1 h:w=1 w:d=2 d:q=2 |
| Silver | E0 E1 E2 E3 | b:h=1 h:w=1 w:d=2 d:q=2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | b:h=1 h:w=1 w:d=2 d:q=2 |
| Decimal8 | E0 E1 E2 E3 | b:h=1 h:w=1 w:d=2 d:q=2 |
| Decimal16 | E0 E1 E2 E3 | b:h=1 h:w=1 w:d=2 d:q=2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
