Difference between revisions of "Instruction Set/fmafn"

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Revision as of 01:29, 3 January 2015

realizing  exu stream  exu block  compute phase   operation   in the binary floating point value domain   and rounds toward negative infinity

native on: Silver Gold

Binary floating point fused multiply-add. As usual for those, it yields a higher precision than doing it separately, and is faster too. Rounds towards negative infinity.


fmafn(f x, f y, f z) → f r0

operands: like Addf [ff:f]

Returns x*y+z on the belt.

encoding: fmafn(f x) , exuArgs(op arg0, op arg1)

Core In Slots Latencies
Silver E0 E1 w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8
Gold E0 E1 E2 E3 w,w:w=6 wv,wv:wv=6 d,d:d=7 dv,dv:dv=7 q,q:q=8 qv,qv:qv=8

fmafn(f x, f y, f z, f w) → f r0, f r1

operands: like Fmasf [ff:f]

This is a fused multiply-add-subtract. An excellent way to make full use of all Functional Units in the 2 Slots.
r0 is x*y+z*w
r1 is x*y-z*w

encoding: fmafn(f x, f y) , exuArgs(op arg0, op arg1)

Core In Slots Latencies
Silver E0 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8
Gold E0 E2 w,w:w,w=6,6 wv,wv:wv,wv=6,6 d,d:d,d=7,7 dv,dv:dv,dv=7,7 q,q:q,q=8,8 qv,qv:qv,qv=8,8


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