Difference between revisions of "Instruction Set/neg"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:neg}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream exu block&...") | |||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
− | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#neg|Tin]] || E0 || 1 |
|- | |- | ||
− | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#neg|Copper]] || E0 E1 || 1 |
|- | |- | ||
− | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#neg|Silver]] || E0 E1 E2 E3 || 1 |
|- | |- | ||
− | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#neg|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1 |
|- | |- | ||
− | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#neg|Decimal8]] || E0 E1 E2 E3 || 1 |
|- | |- | ||
− | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#neg|Decimal16]] || E0 E1 E2 E3 || 1 |
|} | |} | ||
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+ | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] |
Revision as of 02:39, 16 December 2014
realizing exu stream exu block compute phase operation in the logical value domain that produces condition codes
aliases: negs negsv
native on: all
negate
operands: like Identity [xx:x]
Core | In Slots | Latencies |
---|---|---|
Tin | E0 | 1 |
Copper | E0 E1 | 1 |
Silver | E0 E1 E2 E3 | 1 |
Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 1 |
Decimal8 | E0 E1 E2 E3 | 1 |
Decimal16 | E0 E1 E2 E3 | 1 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable