Difference between revisions of "Instruction Set/neq"

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(Created page with "{{DISPLAYTITLE:neq}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing  exu stream  exu block&...")
 
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#681|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#neq|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#681|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#neq|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#681|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#neq|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#681|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#neq|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#681|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#neq|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#681|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#neq|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#682|Tin]] || E0 || 1
+
| [[Cores/Tin/Encoding#neq|Tin]] || E0 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#682|Copper]] || E0 E1 || 1
+
| [[Cores/Copper/Encoding#neq|Copper]] || E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#682|Silver]] || E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#neq|Silver]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#682|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#neq|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#682|Decimal8]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#neq|Decimal8]] || E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#682|Decimal16]] || E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#neq|Decimal16]] || E0 E1 E2 E3 || 1
 
|}
 
|}
  
 
----
 
----
−
<code style="font-size:130%"><b style="color:#050">neq</b>(<span style="color:#666">conditioncode</span>) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
+
<code style="font-size:130%"><b style="color:#050">neq</b>([[Condition_Code|<span style="color:#666">conditioncode</span>]]) &#8594; [[Domains#op|op]] r<sub>0</sub></code>
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
 
</div>
 
</div>
 +
Gets the inequality condition code of the ganged operation and puts it on the belt.
 +
<b>related operations:</b> [[Instruction_Set/eql|eql]], [[Instruction_Set/gtr|gtr]], [[Instruction_Set/geq|geq]], [[Instruction_Set/lss|lss]], [[Instruction_Set/leq|leq]], [[Instruction_Set/carry|carry]], [[Instruction_Set/overflows|overflows]], [[Instruction_Set/fault|fault]]
 
<br />
 
<br />
  
Line 60:Line 62:
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
 
|-
 
|-
−
| [[Cores/Tin/Encoding#680|Tin]] || e0 E0 E1 || 1
+
| [[Cores/Tin/Encoding#neq|Tin]] || e0 E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Copper/Encoding#680|Copper]] || e0 E0 E1 || 1
+
| [[Cores/Copper/Encoding#neq|Copper]] || e0 E0 E1 || 1
 
|-
 
|-
−
| [[Cores/Silver/Encoding#680|Silver]] || e0 E0 E1 E2 E3 || 1
+
| [[Cores/Silver/Encoding#neq|Silver]] || e0 E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Gold/Encoding#680|Gold]] || e0 E0 E1 E2 E3 E4 E5 E6 E7 || 1
+
| [[Cores/Gold/Encoding#neq|Gold]] || e0 E0 E1 E2 E3 E4 E5 E6 E7 || 1
 
|-
 
|-
−
| [[Cores/Decimal8/Encoding#680|Decimal8]] || e0 E0 E1 E2 E3 || 1
+
| [[Cores/Decimal8/Encoding#neq|Decimal8]] || e0 E0 E1 E2 E3 || 1
 
|-
 
|-
−
| [[Cores/Decimal16/Encoding#680|Decimal16]] || e0 E0 E1 E2 E3 || 1
+
| [[Cores/Decimal16/Encoding#neq|Decimal16]] || e0 E0 E1 E2 E3 || 1
 
|}
 
|}
 +
 +
 +
[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]

Revision as of 02:38, 16 December 2014

realizing  exu stream  exu block  compute phase   operation   in the logical value domain  

aliases: neqs nequ
native on: all

not equal

neq(op x, op y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

neq(op x, imm y) → op r0

operands: like Identity [xx:x]


Core In Slots Latencies
Tin E0 1
Copper E0 E1 1
Silver E0 E1 E2 E3 1
Gold E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 E0 E1 E2 E3 1
Decimal16 E0 E1 E2 E3 1

neq(conditioncode) → op r0

operands: like Identity [xx:x]

Gets the inequality condition code of the ganged operation and puts it on the belt. related operations: eql, gtr, geq, lss, leq, carry, overflows, fault

alternate encoding: skinny

Core In Slots Latencies
Tin e0 E0 E1 1
Copper e0 E0 E1 1
Silver e0 E0 E1 E2 E3 1
Gold e0 E0 E1 E2 E3 E4 E5 E6 E7 1
Decimal8 e0 E0 E1 E2 E3 1
Decimal16 e0 E0 E1 E2 E3 1


Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable

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