Difference between revisions of "Instruction Set/widenufv"
From Mill Computing Wiki
(Created page with "{{DISPLAYTITLE:widenufv}} <div style="font-size:80%;line-height:90%;margin-bottom:2em">realizing exu stream Decode|exu blo...") | |||
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! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]] | ||
|- | |- | ||
| − | | [[Cores/Tin/Encoding# | + | | [[Cores/Tin/Encoding#widenufv|Tin]] || E0 || 2 2 |
|- | |- | ||
| − | | [[Cores/Copper/Encoding# | + | | [[Cores/Copper/Encoding#widenufv|Copper]] || E0 E1 || 2 2 |
|- | |- | ||
| − | | [[Cores/Silver/Encoding# | + | | [[Cores/Silver/Encoding#widenufv|Silver]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Gold/Encoding# | + | | [[Cores/Gold/Encoding#widenufv|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal8/Encoding# | + | | [[Cores/Decimal8/Encoding#widenufv|Decimal8]] || E0 E1 E2 E3 || 2 2 |
|- | |- | ||
| − | | [[Cores/Decimal16/Encoding# | + | | [[Cores/Decimal16/Encoding#widenufv|Decimal16]] || E0 E1 E2 E3 || 2 2 |
|} | |} | ||
| + | |||
| + | |||
| + | [[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable] | ||
Revision as of 02:38, 16 December 2014
realizing exu stream exu block compute phase operation in the unsigned fixed point value domain
native on: all
widen to double width
operands: like Widenv XX:2X2X
| Core | In Slots | Latencies |
|---|---|---|
| Tin | E0 | 2 2 |
| Copper | E0 E1 | 2 2 |
| Silver | E0 E1 E2 E3 | 2 2 |
| Gold | E0 E1 E2 E3 E4 E5 E6 E7 | 2 2 |
| Decimal8 | E0 E1 E2 E3 | 2 2 |
| Decimal16 | E0 E1 E2 E3 | 2 2 |
Instruction Set, alphabetical, Instruction Set by Category, Instruction Set, sortable, filterable
