View source for Instruction Set/f2ufixz

{{DISPLAYTITLE:f2ufixz}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the binary floating point value domain]]&nbsp;&nbsp; [[Overflow|using excepting overflow behavior]]&nbsp;&nbsp; [[Condition Code|that produces condition codes]] [[Rounding|and rounds toward zero]]<br />
'''native on:''' [[Cores/Silver|Silver]] <br />
</div>

convert float to unsigned integer
----
<code style="font-size:130%"><b style="color:#050">f2ufixz</b>(<span style="color:#009">[[Domains#f|f]]</span> <span title="belt operand from ops window">op0</span>) &#8594; [[Domains#f|f]] r<sub>0</sub></code>
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeAddf|like Addf [ff:f]]]
</div>
<br />

{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
|-
| [[Cores/Silver/Encoding#f2ufixz|Silver]] || E0 E1 || rw:rw=3 rd:rd=4 rq:rq=5 rvw:rvw=3 rvd:rvd=4 rvq:rvq=5 
|}


[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]