View source for Instruction Set/widens

{{DISPLAYTITLE:widens}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|speculable]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the signed integer value domain]]&nbsp;&nbsp;<br />
'''native on:''' [[Cores|all]]<br />
</div>

Double the scalar width of a signed integer.

Sign extends the upper half.

The natively available byte widths on all [[Cores]] are 1, 2, 4, 8, and on the high end also 16.


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<code style="font-size:130%"><b style="color:#050">widens</b>(<span style="color:#009">[[Domains#s|s]]</span> <span title="belt operand from ops window">v</span>) &#8594; [[Domains#s|s]] r<sub>0</sub></code>
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeWiden|like Widen xx:2x]]
</div>
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
|-
| [[Cores/Tin/Encoding#widens|Tin]] || E0 || b:h=1 h:w=1 w:d=2 d:q=2 
|-
| [[Cores/Copper/Encoding#widens|Copper]] || E0 E1 || b:h=1 h:w=1 w:d=2 d:q=2 
|-
| [[Cores/Silver/Encoding#widens|Silver]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=2 d:q=2 
|-
| [[Cores/Gold/Encoding#widens|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:h=1 h:w=1 w:d=2 d:q=2 
|-
| [[Cores/Decimal8/Encoding#widens|Decimal8]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=2 d:q=2 
|-
| [[Cores/Decimal16/Encoding#widens|Decimal16]] || E0 E1 E2 E3 || b:h=1 h:w=1 w:d=2 d:q=2 
|}


[[Instruction_Set|Instruction Set, alphabetical]], [[Instruction Set by Category]], [http://millcomputing.com/instructions.html?collapse=7#ops Instruction Set, sortable, filterable]