View source for Instruction Set/rdivu

{{DISPLAYTITLE:rdivu}}
<div style="font-size:80%;line-height:90%;margin-bottom:2em">[[Speculation|realizing]]&nbsp;&nbsp;[[Encoding|exu stream]]&nbsp;&nbsp;[[Decode|exu block]]&nbsp;&nbsp;[[Phasing|compute phase]]&nbsp;&nbsp; operation&nbsp;&nbsp; [[Domains|in the unsigned integer value domain]]&nbsp;&nbsp;<br />
'''native on:''' [[Cores|all]]<br />
</div>

Unsigned integer reciprocal dividion. Helper operation for software division implementation.

This operation creates a seed value for Newton-Rapheson, or other, iterative division.

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<code style="font-size:130%"><b style="color:#050">rdivu</b>(<span style="color:#009">[[Domains#u|u]]</span> <span title="belt operand from ops window">x</span>) &#8594; [[Domains#u|u]] r<sub>0</sub></code>
<div style="font-size:80%;line-height:90%;margin-bottom:2em">'''operands:''' [[Operands#likeIdentity|like Identity [xx:x]]]
</div>
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{| class="mw-collapsible mw-collapsed wikitable" data-expandtext="&#9656;" data-collapsetext="&#9662;"
! [[Cores|Core]] || [[Slot|In Slots]]|| [[Latency|Latencies]]
|-
| [[Cores/Tin/Encoding#rdivu|Tin]] || E0 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 
|-
| [[Cores/Copper/Encoding#rdivu|Copper]] || E0 E1 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 
|-
| [[Cores/Silver/Encoding#rdivu|Silver]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 
|-
| [[Cores/Gold/Encoding#rdivu|Gold]] || E0 E1 E2 E3 E4 E5 E6 E7 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 
|-
| [[Cores/Decimal8/Encoding#rdivu|Decimal8]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 
|-
| [[Cores/Decimal16/Encoding#rdivu|Decimal16]] || E0 E1 E2 E3 || b:b=1 bv:bv=1 h:h=1 hv:hv=1 w:w=1 wv:wv=1 d:d=2 dv:dv=2 q:q=2 qv:qv=2 
|}


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